View DS1859E-015_9098981.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds1859 dual, temperature-controlled resistors with internally calibrated monitors ______________________________________________ maxim integrated products 1 for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the ds1859 dual, temperature-controlled, nonvolatile(nv) variable resistors with three monitors consists of two 50k ? or two 20k ? , 256-position, linear, variable resistors; three analog monitor inputs (mon1, mon2,mon3); and a direct-to-digital temperature sensor. the device provides an ideal method for setting and tem- perature-compensating bias voltages and currents in control applications using minimal circuitry. the vari- able resistor settings are stored in eeprom memory and can be accessed over the 2-wire serial bus. applications optical transceiversoptical transponders instrumentation and industrial controls rf power amps diagnostic monitoring features ? sff-8472 compatible ? five monitored channels (temperature, v cc , mon1, mon2, mon3) ? three external analog inputs (mon1, mon2, mon3)that support internal and external calibration ? scalable dynamic range for external analog inputs ? internal direct-to-digital temperature sensor ? alarm and warning flags for all monitoredchannels ? two 50k ? or two 20k ? , linear, 256-position, nonvolatile temperature-controlled variableresistors ? resistor settings changeable every 2c ? access to monitoring and id informationconfigurable with separate device addresses ? 2-wire serial interface ? two buffers with ttl/cmos-compatible inputs andopen-drain outputs ? operates from a 3.3v or 5v supply ? operating temperature range of -40? to +95? ordering information rev 4; 2/06 evaluation kit available part resistance pin-package ds1859b-020 20k ? 16 csbga ds1859b-020+ 20k ? 16 csbga ds1859b-050 50k ? 16 csbga ds1859b-050+ 50k ? 16 csbga a top view b cd 1 csbga (4mm x 4mm) 1.0mm pitch tssop 3 24 mon3 out1 in2 mon1 l0 gnd wpen l1 h0 sda out2 h1 v cc scl in1 mon2 ds1859 sda 12 3 4 5 6 7 8 16 1514 13 12 11 10 9 sclout1 in1 out2 in2 wpen gnd v cc h1 l1 h0 l0 mon3mon2 mon1 pin configurations ds1859 sda 12 3 4 5 6 7 8 16 0.1 f 1514 13 12 11 10 9 sclout1 in1 out2 in2 wpen gnd v cc h1 l1 h0 l0 mon3mon2 mon1 ground to disable write protect rx power* diagnostic inputs to laser modulation control to laser biascontrol decouplingcap tx power*tx bias* *satisfies sff-8472 compatibility v cc v cc = 3.3v 4.7k ? 4.7k ? tx-fault los 2-wire interface t ypical operating circuit + denotes lead-free package. ordering information continued at end of data sheet. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 2 _____________________________________________________________________ parameter symbol conditions min typ max units supply voltage v cc (note 1) 2.85 5.5 v input logic 1 (sda, scl, wpen) v ih (note 2) 0.7 x vcc v cc + 0.3 v input logic 0 (sda, scl, wpen) v il (note 2) -0.3 +0.3 x v cc v resistor inputs (l0, l1, h0, h1) -0.3 v cc + 0.3 v resistor current i res -3 +3 ma high-z resistor current i roff 0.001 0.1 ? input logic 1 1.5 input logic levels (in1, in2) input logic 0 0.9 v absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on v cc relative to ground ...........-0.5v to +6.0v voltage range on inputs relative to ground* ................................................-0.5v to v cc + 0.5v voltage range on resistor inputs relative to ground* ................................................-0.5v to v cc + 0.5v current into resistors............................................................5ma operating temperature range ...........................-40? to +95? programming temperature range .........................0? to +70? storage temperature range .............................-55? to +125? soldering temperature .......................................see ipc/jedec j-std-020a recommended dc operating conditions(t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units supply current i cc (note 3) 1 2 ma input leakage i il -200 +200 na v ol1 3ma sink current 0 0.4 low-level output voltage(sda, out1, out2) v ol2 6ma sink current 0 0.6 v full-scale input (mon1, mon2,mon3) at factory setting(note 4) 2.4875 2.5 2.5125 v full-scale v cc monitor at factory setting(note 5) 6.5208 6.5536 6.5864 v i/o capacitance c i/o 10 pf wpen pullup r wpen 40 65 100 k ? digital power-on reset pod 1.0 2.2 v analog power-on reset poa 2.0 2.6 v dc electrical characteristics(v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) * not to exceed 6.0v. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors _____________________________________________________________________ 3 parameter symbol conditions min typ max units thermometer error t err -40? to +95? 3.0 ? digital thermometer(v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units eeprom writes +70? 50,000 nonvolatile memory characteristics (v cc = 2.85v to 5.5v) parameter symbol conditions min typ max units input resolution ? vmon 610 ? supply resolution ? v cc 1.6 mv input/supply accuracy(mon1, mon2, mon3, v cc ) a cc at factory setting 0.25 0.5 % fs (full scale) update rate for mon1, mon2,mon3, temp, or v cc t frame 30 45 ms input/supply offset(mon1, mon2, mon3, v cc ) v os (note 14) 0 5 lsb analog voltage monitoring (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) parameter symbol conditions min typ max units position 00h resistance (50k ? )t a = +25? 0.65 1.0 1.35 k ? position ffh resistance (50k ? )t a = +25? 40 50 60 k ? position 00h resistance (20k ? )t a = +25? 0.20 0.40 0.55 k ? position ffh resistance (20k ? )t a = +25? 16 20 24 k ? absolute linearity (note 6) -2 +2 lsb relative linearity (note 7) -1 +1 lsb temperature coefficient (note 8) 50 ppm/? analog resistor characteristics (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted.) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 4 _____________________________________________________________________ parameter symbol conditions min typ max units fast mode (note 9) 0 400 scl clock frequency f scl standard mode (note 9) 0 100 khz fast mode (note 9) 1.3 bus free time between stop andstart condition t buf standard mode (note 9) 4.7 ? fast mode (notes 9, 10) 0.6 hold time (repeated)start condition t hd:sta standard mode (notes 9, 10) 4.0 ? fast mode (note 9) 1.3 low period of scl clock t low standard mode (note 9) 4.7 ? fast mode (note 9) 0.6 high period of scl clock t high standard mode (note 9) 4.0 ? fast mode (notes 9, 11, 12) 0 0.9 data hold time t hd:dat standard mode (notes 9, 11, 12) 0 ? fast mode (note 9) 100 data setup time t su:dat standard mode (note 9) 250 ns fast mode (note 9) 0.6 start setup time t su:sta standard mode (note 9) 4.7 ? fast mode (note 13) 20 + 0.1c b 300 rise time of both sda and sclsignals t r standard mode (note 13) 20 + 0.1c b 1000 ns fast mode (note 13) 20 + 0.1c b 300 fall time of both sda and sclsignals t f standard mode (note 13) 20 + 0.1c b 300 ns fast mode 0.6 setup time for stop condition t su:sto standard mode 4.0 ? capacitive load for each bus line c b (note 13) 400 pf eeprom write time t w (note 14) 10 20 ms ac electrical characteristics (v cc = 2.85v to 5.5v, t a = -40? to +95?, unless otherwise noted. see figure 6.) note 1: all voltages are referenced to ground. note 2: i/o pins of fast-mode devices must not obstruct the sda and scl lines if v cc is switched off. note 3: sda and scl are connected to v cc and all other input signals are connected to well-defined logic levels. note 4: full scale is user programmable. the maximum voltage that the mon inputs read is approximately full scale, even if the volt- age on the inputs is greater than full scale. note 5: this voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum v cc voltage. note 6: absolute linearity is the difference of measured value from expected value at dac position. the expected value is astraight line from measured minimum position to measured maximum position. note 7: relative linearity is the deviation of an lsb dac setting change vs. the expected lsb change. the expected lsb changeis the slope of the straight line from measured minimum position to measured maximum position. note 8: see the typical operating characteristics . note 9: a fast-mode device can be used in a standard-mode system, but the requirement t su:dat > 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000ns + 250ns = 1250ns before the scl line is released. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors _____________________________________________________________________ 5 note 10: after this period, the first clock pulse is generated. note 11: the maximum t hd:dat only has to be met if the device does not stretch the low period (t low ) of the scl signal. note 12: a device must internally provide a hold time of at least 300ns for the sda signal (see the v ih min of the scl signal) to bridge the undefined region of the falling edge of scl. note 13: c b ?otal capacitance of one bus line, timing referenced to 0.9 x v cc and 0.1 x v cc . note 14: guaranteed by design. t ypical operating characteristics (v cc = 5.0v, t a = +25?, for both 50k ? and 20k ? versions, unless otherwise noted.) temperature ( c) 40 60 80 20 0 -20 560 600 640 680 720520 -40 100 supply current vs. temperature ds1859 toc01 supply current ( a) sda = scl = v cc supply current vs. voltage ds1859 toc02 voltage (v) supply current ( a) 5.0 4.5 4.0 3.5 450 500 550 600 650 700400 3.0 5.5 sda = scl = v cc resistance vs. setting ds1859 toc03 setting (dec) resistance (k ? ) 200 150 100 50 10 20 30 40 50 60 0 0 250 50k ? version resistance vs. setting ds1859 toc04 setting (dec) resistance (k ? ) 200 150 100 50 5 10 15 20 0 0 250 20k ? version active supply current vs. scl frequency ds1859 toc05 scl frequency (khz) active supply current ( a) 300 200 100 600 640 680 720 760560 0 400 sda = v cc resistor 0 inl (lsb) ds1859 toc06 setting (dec) resistor 0 inl (lsb) 225 200 150 175 50 75 100 125 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 250 downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 6 _____________________________________________________________________ t ypical operating characteristics (continued) (v cc = 5.0v, t a = +25?, for both 50k ? and 20k ? versions, unless otherwise noted.) resistor 0 dnl (lsb) ds1859 toc07 setting (dec) resistor 0 dnl (lsb) 225 200 150 175 50 75 100 125 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 250 resistor 1 inl (lsb) ds1859 toc08 setting (dec) resistor 1 inl (lsb) 225 200 150 175 50 75 100 125 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 250 resistor 1 dnl (lsb) ds1859 toc09 setting (dec) resistor 1 dnl (lsb) 225 200 150 175 50 75 100 125 25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 250 position 00h resistance vs. temperature ds1859 toc12 temperature ( c) resistance (k ? ) 20 35 50 65 80 5 -10 -25 0.96 0.97 0.98 0.99 1.000.95 -40 95 50k ? version resistance vs. power-up voltage ds1859 toc11 power-up voltage (v) resistance (k ? ) 234 1 3020 40 50 60 70 80 90 100 110 120 0 10 05 programmed resistance (80h) >1m ? 20k ? version resistance vs. power-up voltage ds1859 toc10 power-up voltage (v) resistance (k ? ) 234 1 3020 40 50 60 70 80 90 100 110 120 0 10 05 programmed resistance (80h) >1m ? 50k ? version downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors _______________________________________________________________________________________ 7 t ypical operating characteristics (continued) (v cc = 5.0v, t a = +25?, for both 50k ? and 20k ? versions, unless otherwise noted.) position ffh resistance vs. temperature ds1859 toc14 temperature ( c) resistance (k ? ) 80 65 50 35 20 5 -10 -25 51.20 51.40 51.60 51.80 52.0051.00 -40 95 50k ? version position ffh resistance vs. temperature ds1859 toc15 temperature ( c) resistance (k ? ) 80 65 50 35 20 5 -10 -25 19.20 19.40 19.50 19.80 20.0019.00 -40 95 20k ? version temperature coefficient vs. setting ds1859 toc16 setting (dec) temperature coefficient (ppm/ c) 200 150 100 50 100 50 0 -50 150 200 250 300 350 400 -100 0 250 50k ? version +25 c to +95 c +25 c to -40 c temperature coefficient vs. setting ds1859 toc17 setting (dec) temperature coefficient (ppm/ c) 200 150 100 50 100 0 200 300 400 500 600 700 800 -100 0 250 +25 c to +95 c +25 c to -40 c 20k ? version lsb error vs. full-scale input ds1859 toc18 normalized full scale (%) lsb error 75 50 25 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 -8 0 100 +3 sigma -3 sigma mean lsb error vs. full-scale input ds1859 toc19 normalized full scale (%) lsb error 9.375 6.250 3.125 -3 -2 -1 0 1 2 3 -4 0 12.500 +3 sigma -3 sigma mean position 00h resistance vs. temperature ds1859 toc13 temperature ( c) resistance (k ? ) 80 65 50 35 20 5 -10 -25 0.34 0.35 0.36 0.37 0.380.33 -40 95 20k ? version downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 8 _____________________________________________________________________ detailed description the user can read the registers that monitor the v cc , mon1, mon2, mon3, and temperature analog signals.after each signal conversion, a corresponding bit is set that can be monitored to verify that a conversion has occurred. the signals also have alarm and warning flags that notify the user when the signals go above or below the user-defined value. interrupts can also be set for each signal. the position values of each resistor can be indepen- dently programmed. the user can assign a unique value to each resistor for every 2? increment over the -40? to +102? range. two buffers are provided to convert logic-level inputsinto open-drain outputs. typically, these buffers are used to implement transmit (tx) fault and loss-of-signal (los) functionality. additionally, out1 can be asserted in the event that one or more of the monitored values go beyond user-defined limits. pin ball name function 1b 2 sda 2-wire serial data i/o pin. transfers serial data to and from the device. 2a 2 scl 2-wire serial clock input. clocks data into and out of the device. 3c 3 out1 open-drain buffer output 4a 1 in1 ttl/cmos-compatible input to buffer 5b 1 out2 open-drain buffer output 6c 2 in2 ttl/cmos-compatible input to buffer 7c 1 wpen write protect enable. the device is not write protected if wpen is connected to ground. this pin has an internal pullup (r wpen ). see table 6. 8d 1 gnd ground 9d 3 mon1 external analog input 10 d4 mon2 external analog input 11 c4 mon3 external analog input 12 d2 l0 low-end resistor 0 terminal. it is not required that the low-end terminals be connected to a potentialless than the high-end terminals of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 13 b3 h0 high-end resistor 0 terminal. it is not required that the high-end terminals be connected to apotential greater than the low-end terminals of the corresponding resistor. voltage applied to any of the resistor terminals cannot exceed the power-supply voltage, v cc , or go below ground. 14 b4 l1 low-end resistor 1 terminal 15 a4 h1 high-end resistor 1 terminal 16 a3 v cc supply voltage pin description downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors _____________________________________________________________________ 9 device address ad (auxiliary device enable a0h) md (main device enable) device addressaddress address address r/w r/w txf data bus r/w txf rxl los aden adfix sda scl in1 out1 2-wire interface mint inv1 tx fault in2 mon2 mon1 mon3 v cc gnd wpen out2 inv2 eeprom 128 x 8 bit 00h-7fh standards prot aux ad address table select r/w eeprom 72 x 8 bit 80h-c7h table 02 resistor 0 look-up table protmain md eeprom 96 x 8 bit 00h-5fh limits sram 32 x 8 bit 60h-7fh not protected protmain md temp index alarm flags warning flags mux ctrl measurement address table select r/w eeprom 72 x 8 bit 80h-c7h table 03 resistor 1 look-up table protmain md temp index r wpen monitors limit high monitors limit low table select temp index mint (bit) internal temp v cc mux adc 12-bit internal calibration a/d ctrl v cc v cc prot auxprot main mpen apen comparator measurement alarm flags warning flags monitors limit low monitors limit high comp ctrl interrupt mint table 01 eeprom 16 x 8 bit 80h-8fh vendor protmain md r/w device address address table select masking (tmp, v cc , mon1, mon2, mon3) adfix (bit) aden (bit) mpen (bit) apen (bit) inv2 (bit) inv1 (bit) resistor 050k ? or 20k ? full scale 256 positions l0 h0 register register resistor 150k ? or 20k ? full scale 256 positions l1 h1 right shifting ds1859 figure 1. block diagram downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 10 ____________________________________________________________________ monitored signals each signal (v cc , mon1, mon2, mon3, and tempera- ture) is available as a 16-bit value with 12-bit accuracy (left-justified) over the serial bus. see table 1 for signal scales and table 2 for signal format. the four lsbs should be masked when calculating the value. for the 20k ? version, the 3 lsbs are internally masked with 0s.the signals are updated every frame rate (t frame ) in a round-robin fashion.the comparison of all five signals with the high and low user-defined values are done automatically. the corre- sponding flags are set to 1 within a specified time of the occurrence of an out-of-limit condition. calculating signal values the lsb = 100? for v cc , and the lsb = 38.147? for the mon signals when using factory default settings. to calculate v cc , convert the unsigned 16-bit value to decimal and multiply by 100?.to calculate mon1, mon2, or mon3, convert the unsigned 16-bit value to decimal and multiply by 38.147?. to calculate the temperature, treat the two? comple- ment value binary number as an unsigned binary num- ber, then convert to decimal and divide by 256. if the result is greater than or equal to 128, subtract 256 from the result. temperature: high byte: -128 c to +127 c signed; low byte: 1/256 c. signal +fs signal +fs ( hex) -fs signal -fs ( hex) temperature 127.984 c 7ffc -128 c 8000 v cc 6.5528v fff8 0v 0000 mon1 2.4997v fff8 0v 0000 mon2 2.4997v fff8 0v 0000 mon3 2.4997v fff8 0v 0000 table 1. scales for monitor channels atfactory setting signal format v cc unsigned mon1 unsigned mon2 unsigned mon3 unsigned temperature two? complement table 2. signal comparison temperature (?) corresponding look-up table address <-40 80h -40 80h -38 81h -36 82h -34 83h +98 c5h +100 c6h +102 c7h >+102 c7h table 3. look-up table address forcorresponding temperature values msb 2 15 2 14 2 13 2 12 2 11 2 10 2 9 2 8 lsb 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 msb (bin) lsb (bin) voltage (v) 10000000 10000000 3.29 11000000 11111000 4.94 s2 6 2 5 2 4 2 3 2 2 2 1 2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 msb (bin) lsb (bin) temperature ( c) 01000000 00000000 64 01000000 00001111 64.059 01011111 00000000 95 11110110 00000000 -10 11011000 00000000 -40 msb (bin) lsb (bin) voltage (v) 11000000 00000000 1.875 10000000 10000000 1.255 monitor/v cc bit weights temperature bit weights monitor conversion example v cc conversion examples temperature conversion examples downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 11 variable resistors the value of each variable resistor is determined bya temperature-addressed look-up table, which can assign a unique value (00h to ffh) to each resistor for every 2? increment over the -40? to +102? range (see table 3). see the temperature conversion section for more information.the variable resistors can also be used in manual mode. if the ten bit equals 0, the resistors are in manu- al mode and the temperature indexing is disabled. the user sets the resistors in manual mode by writing to addresses 82h and 83h in table 01 to control resistors 0 and 1, respectively. memory description main and auxiliary memories can be accessed by twoseparate device addresses. the main device address is a2h (or value in table 01 byte 8ch, when adfix = 1) and the auxiliary device address is a0h. a user option is provided to respond to one or two device addresses. this feature can be used to save component count in sff applications (main device address can be used) or other applications where both gbic (auxiliary device address can be used) and monitoring functions are implemented and two device addresses are need- ed. the memory blocks are enabled with the corre- sponding device address. memory space from 80h and aden (address enable) no. of separate device addresses additional information 02 see figure 2 1 1 (main device only) see figure 3 table 4. aden address configuration aden adfix auxiliary address main address 00 a0h a2h 01 a0h eeprom (table 01, 8ch) 10 n/a a2h 11 n/a eeprom (table 01, 8ch) table 5. aden and adfix bits main device mon look-up table control r0 look-up table auxiliary device 0 dec 0 9596 127128 143 199 memory partition with aden bit = 0 en en en 5fh 60h en sel en sel 7fh 7fh 80h 80h c7h f0h ffh reserved 8fh table select main device enable auxiliary device enable decoder 0 f0h ffh reserved r1 look-up table en sel 80h c7h table 03 table 02 table 01 figure 2. memory organization, aden = 0 downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 12 ____________________________________________________________________ above is accessible only through the main deviceaddress. this memory is organized as three tables. the desired table can be selected by the contents of mem- ory location 7fh, main device. the auxiliary device address has no access to the tables, but the auxiliary device address can be mapped into the main device? memory space as a fourth table. device addresses are programmable with two control bits in eeprom. aden configures memory access to respond to differ- ent device addresses (see tables 4 and 5). the default device address for eeprom-generated addresses is a2h. if the aden bit is 1, additional 128 bytes of eeprom are accessible through the main device, selected as table 00 (see figure 3). in this configuration, the auxiliary device is not accessible. apen controls the protection of table 00 regardless of aden? setting. adfix (address fixed) determines whether the main device address is determined by an eeprom byte (table 01, byte 8ch, when adfix = 1). there can be up to 128 devices sharing a common 2-wire bus, with each device having its own unique device address. wpen mpen protect main 0x n o x0 n o 11 yes table 6. main device apen wpen protect auxiliary 0 xn o 1 x yes table 7. auxiliary device main device mon look-up table control r0 look-up table auxiliary device 80h dec 0 9596 127128 143 199 255 en en en 5fh 60h en sel en sel ffh 7fh 80h 80h c7h f0h ffh reserved 8fh table select table 00 main device enable decoder 0 f0h ffh reserved r1 look-up table en sel 80h c7h table 03 table 02 table 01 memory partition with aden bit = 1 figure 3. memory organization, aden = 1 downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 13 memory location ( hex) eeprom/sram r/w default setting ( hex) name of location function 00 to 7f eeprom r/w 00 standards data auxiliary device memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 00 to 01 eeprom r/w 00 tmplimhi (msb to lsb) contains upper limit settings for temperature.if the limit is violated, an alarm flag in main device byte 70h is set. 02 to 03 eeprom r/w 00 tmplimlo (msb to lsb) contains lower limit settings for temperature. ifthe limit is violated, an alarm flag in main device byte 70h is set. 04 to 05 eeprom r/w 00 tmpwrnhi (msb to lsb) contains upper limit settings for temperature.if the limit is violated, a warning flag in main device byte 74h is set. 06 to 07 eeprom r/w 00 tmpwrnlo (msb to lsb) contains lower limit settings for temperature. ifthe limit is violated, a warning flag in main device byte 74h is set. 08 to 09 eeprom r/w 00 v cc limhi (msb to lsb) contains upper limit settings for v cc . if the limit is violated, an alarm flag in main devicebyte 70h is set. 0a to 0b eeprom r/w 00 v cc limlo (msb to lsb) contains lower limit settings for v cc . if the limit is violated, an alarm flag in main devicebyte 70h is set. 0c to 0d eeprom r/w 00 v cc wrnhi (msb to lsb) contains upper limit settings for v cc . if the limit is violated, a warning flag in main devicebyte 74h is set. 0e to 0f eeprom r/w 00 v cc wrnlo (msb to lsb) contains lower limit settings for v cc . if the limit is violated, a warning flag in main devicebyte 74h is set. 10 to 11 eeprom r/w 00 mon1limhi (msb to lsb) contains upper limit settings for mon1. if thelimit is violated, an alarm flag in main device byte 70h is set. main device note: sram defaults are power-on defaults. eeprom defaults are factory defaults. register map a description of the registers is below. the registersare read only (r) or read/write (r/w). the r/w registers are writable only if write protect has not been asserted (see the memory description section). bytes designated as "reserved" have been set asidefor added functionality in future revisions of this device. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 14 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 12 to 13 eeprom r/w 00 mon1limlo (msb to lsb) contains lower limit settings for mon1. if thelimit is violated, an alarm flag in main device byte 70h is set. 14 to 15 eeprom r/w 00 mon1wrnhi (msb to lsb) contains upper limit settings for mon1. if thelimit is violated, a warning flag in main device byte 74h is set. 16 to 17 eeprom r/w 00 mon1wrnlo (msb to lsb) contains lower limit settings for mon1. if thelimit is violated, a warning flag in main device byte 74h is set. 18 to 19 eeprom r/w 00 mon2limhi (msb to lsb) contains upper limit settings for mon2. if thelimit is violated, an alarm flag in main device byte 70h is set. 1a to 1b eeprom r/w 00 mon2limlo (msb to lsb) contains lower limit settings for mon2. if thelimit is violated, an alarm flag in main device byte 70h is set. 1c to 1d eeprom r/w 00 mon2wrnhi (msb to lsb) contains upper limit settings for mon2. if thelimit is violated, a warning flag in main device byte 74h is set. 1e to 1f eeprom r/w 00 mon2wrnlo (msb to lsb) contains lower limit settings for mon2. if thelimit is violated, a warning flag in main device byte 74h is set. 20 to 21 eeprom r/w 00 mon3limhi (msb to lsb) contains upper limit settings for mon3. if thelimit is violated, an alarm flag in main device byte 71h is set. 22 to 23 eeprom r/w 00 mon3limlo (msb to lsb) contains lower limit settings for mon3. if thelimit is violated, an alarm flag in main device byte 71h is set. 24 to 25 eeprom r/w 00 mon3wrnhi (msb to lsb) contains upper limit settings for mon3. if thelimit is violated, a warning flag in main device byte 75h is set. 26 to 27 eeprom r/w 00 mon3wrnlo (msb to lsb) contains lower limit settings for mon3. if thelimit is violated, a warning flag in main device byte 75h is set. 28 to 37 eeprom reserved 38 to 5f eeprom r/w memory 60 to 61 sram r measured tmp (msb to lsb) digitized measured value for temperature.see table 1. 62 to 63 sram r measured v cc (msb to lsb) digitized measured value for v cc . see table 1. 64 to 65 sram r measured mon1 (msb to lsb) digitized measured value for mon1.see table 1. 66 to 67 sram r measured mon2 (msb to lsb) digitized measured value for mon2.see table 1. main device (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 15 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 68 to 69 sram r measured mon3 (msb to lsb) digitized measured value for mon3.see table 1. 6a to 6d sram reserved 6e sram logic states bit 7 r x hizsta resistor status bit. a high indicates that bothresistors are in high-impedance mode. a low indicates that both resistors are operating normally. 6 r/w 0 hizco resistor control bit. setting this bit highcauses both resistors to go into a high- impedance state. 5 x x 4 x x 3 x x 2r x txf this status bit is high when out1 is high,assuming there is an external pullup resistor on out1. 1r x rxl this status bit is high when out2 is high,assuming there is an external pullup resistor on out2. 0 rx rdyb this status bit goes high when v cc has fallen below the poa level. 6f sram conversion updates bit 7 r/w 0 tau this bit goes high after a temperature andaddress update has occurred for the corresponding measurement in bytes 60h to 61h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 6 r/w 0v cc u this bit goes high after a v cc update has occurred for the corresponding measurementin bytes 62h to 63h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 5 r/w 0 mon1u this bit goes high after a mon1 update hasoccurred for the corresponding measurement in bytes 64h to 65h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. main device (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 16 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 4 r/w 0 mon2u this bit goes high after a mon2 update hasoccurred for the corresponding measurement in bytes 66h to 67h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 3 ? mon3u this bit goes high after a mon3 update hasoccurred for the corresponding measurement in bytes 68h to 69h. this bit can be written to a 0 by the user and monitored to verify that a conversion has occurred. 2 0 1 0 0 0 70 sram r alarm flags bit 7 tmphi this alarm flag goes high when the upper limitof the temperature setting is violated. 6 tmplo this alarm flag goes high when the lower limitof the temperature setting is violated. 5 v cc hi this alarm flag goes high when the upper limitof the v cc setting is violated. 4 v cc lo this alarm flag goes high when the lower limitof the v cc setting is violated. 3 mon1hi this alarm flag goes high when the upper limitof the mon1 setting is violated. 2 mon1lo this alarm flag goes high when the lower limitof the mon1 setting is violated. 1 mon2hi this alarm flag goes high when the upper limitof the mon2 setting is violated. 0 mon2lo this alarm flag goes high when the lower limitof the mon2 setting is violated. 71 sram r alarm flags bit 7 mon3hi this alarm flag goes high when the upper limitof the mon3 setting is violated. 6 mon3lo this alarm flag goes high when the lower limitof the mon3 setting is violated. 5 x 4 x main device (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 17 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 3 x 2 x 1 x 0 mint a mask of all flags located in table 01 byte88h determines the value of mint. mint is maskable to 0 if no interrupt is desired by setting table 01 byte 88h to 0. 72 to 73 sram reserved 74 sram r warning flags bit 7 tmphi this warning flag goes high when the upperlimit of the temperature setting is violated. 6 tmplo this warning flag goes high when the lowerlimit of the temperature setting is violated. 5 v cc hi this warning flag goes high when the upperlimit of the v cc setting is violated. 4 v cc lo this warning flag goes high when the lowerlimit of the v cc setting is violated. 3 mon1hi this warning flag goes high when the upperlimit of the mon1 setting is violated. 2 mon1lo this warning flag goes high when the lowerlimit of the mon1 setting is violated. 1 mon2hi this warning flag goes high when the upperlimit of the mon2 setting is violated. 0 mon2lo this warning flag goes high when the lowerlimit of the mon2 setting is violated. main device (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 18 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 75 sram r warning flags bit 7 0 mon3hi this warning flag goes high when the upperlimit of the mon3 setting is violated. 6 ? mon3lo this warning flag goes high when the lowerlimit of the mon3 setting is violated. 5 0 x 4 0 x 3 0 x 2 0 x 1 0 x 76 to 7e sram reserved 7f sram r/w table select bit 7 0 x 6 0 x 5 0 x 4 0 x 3 0 x 2 0 x 1 0 0 0 table select bits set bits = 00 to select table 00, set bits = 01to select table 01, set bits = 10 to select table 02, set bits = 11 to select table 03. main device (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 19 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 sram r/w mode bit 7 0 x 6? x 5? x 4? x 3? x 2? x 1? ten if ten = 0, the resistors can be controlled manually. theuser sets the resistor in manual mode by writing to addresses 82h and 83h in table 01 to control resistors 0 and 1, respectively. 0? aen aen = 0 is a test mode setting and provides manual control of the temperature index (table 01, address 81h). 81 sram r temperature index this byte is the temperature-calculated index used toselect the address of resistor settings in the look-up tables (tables 02 and 03, addresses 80h through c7h). 82 sram r/w ff resistor 0 resistor 0 position values from 00h to ffh. 83 sram r/w ff resistor 1 resistor 1 position values from 00h to ffh. 84 to 87 sram reserved 88 eeprom r/w interrupt enable this byte configures a maskable interrupt, determining which event asserts a buffer 1 output (mint set to 1, see register 89h in table 01). if any combination of temperature, v cc , mon1, mon2, or mon3 is desired to generate an interrupt, the corresponding bits are set to 1.if interrupt generation is not desired, set all bits to 0. bit 7 1 tmp 6? v cc 5 ? mon1 4 ? mon2 3 ? mon3 2? x 1? x 0? x 89 eeprom r/w configuration bit 7 0 x 6? x table 01h downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 20 ____________________________________________________________________ memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 5 ? aden controls if the device responds to one or two deviceaddresses (see the memory description section and table 5). 4 ? adfix controls the means by which main and auxiliary deviceaddresses are set (see the memory description section and table 5). 3 ? apen controls auxiliary write protect. see the memory description section. 2 ? mpen controls main write protect. see the memory description section. 1 ? inv1 configures buffer 1 with out1 = mint +(inv1 [xor] in1). 0 ? inv2 configures buffer 2 with out2 = inv2 [xor] in2. 8a to 8b eeprom reserved 8c eeprom r/w a2 device address contains main device address if the bit adfix = 1. ifadfix = 0, then address a2h is used. 8d eeprom reserved 8e eeprom r/w contains bits used to perform right shift operations on thea/d output converter. see the right shift a/d conversion result section. 7? 6 ? mon1 2 right shift control msb 5 ? mon1 1 4 ? mon1 0 right shift control lsb 3? 2 ? mon2 2 right shift control msb 1 ? mon2 1 0 ? mon2 0 right shift control lsb 8f eeprom r/w contains bits used to perform right shift operations on thea/d output converter. see the right shift a/d conversion result section. 7? 6 ? mon3 2 right shift control msb 5 ? mon3 1 4 ? mon3 0 right shift control lsb 3? 2? 1? 0? table 01h (continued) downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 21 memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 90 to 91 eeprom ? reserved 92 to 93 eeprom r/w gain cal v cc gain registers for internal calibration. see the internal calibration section. 94 to 95 eeprom r/w gain cal mon1 96 to 97 eeprom r/w gain cal mon2 98 to 99 eeprom r/w gain cal mon3 9a to 9f eeprom reserved a0 to a1 eeprom reserved a2 to a3 eeprom r/w offset cal v cc offset registers for internal calibration.see the internal calibration section. a4 to a5 eeprom r/w offset cal mon1 a6 to a7 eeprom r/w offset cal mon2 a8 to a9 eeprom r/w offset cal mon3 aa to ad eeprom reserved ae to af eeprom r/w factory programmed offset cal tmp offset calibration for temperature calibrated at factory. table 01h (continued) memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 to c7 eeprom r/w ff resistor 0 temp lut look-up table for resistor 0. f0 to f7 eeprom reserved f8 to ff eeprom r factory programmed resistor 0 cal constants calibration constants for resistor 0.(see table 8) table 02h memory location ( hex) eeprom/ sram r/w default setting ( hex) name of location function 80 to c7 eeprom r/w ff resistor 1 temp lut look-up table for resistor 1. f0 to f7 eeprom reserved f8 to ff eeprom r factory programmed resistor 1 cal constants calibration constants for resistor 1.(see table 8) table 03h downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 22 ____________________________________________________________________ programming the look-up table (lut) the following equation can be used to determine whichresistor position setting, 00h to ffh, should be written in the lut to achieve a given resistance at a specific tem- perature. = 3.852357 for the 20k ? resistor = 4.5680475 for the 50k ? resistor r = the resistance desired at the output terminalc = temperature in degrees celsius u, v, w, x 1 , x 0 , y, and z are calculated values found in the corresponding look-up tables. the variable x from theequation above is separated into x 1 (the msb of x) and x 0 (the lsb of x). their addresses and lsb values are givenbelow. resistor 0 variables are found in table 1, and resistor 1 variables are found in table 2. when shipped from the factory, all other memory loca- tions in the luts are programmed to ffh. table 8. calibration constants internal calibration the ds1859 has two methods for scaling an analoginput to a digital result. the two methods are gain and offset. each of the inputs (v cc , mon1, mon2, and mon3) has a unique register for the gain and the offset found in table 01h, 92h to 99h, and a2h to a9h. to scale the gain and offset of the converter for a spe- cific input, you must first know the relationship between the analog input and the expected digital result. the input that would produce a digital result of all zeros is the null value (normally this input is gnd). the input that would produce a digital result of all ones is the full- scale (fs) value. the fs value is also found by multiply- ing an all-ones digital answer by the weighted lsb (e.g., since the digital reading is a 16-bit register, let us assume that the lsb of the lowest weighted bit is50?, then the fs value is 65,535 x 50? = 3.27675v). a binary search is used to scale the gain of the con- verter. this requires forcing two known voltages to the input pin. it is preferred that one of the forced voltages is the null input and the other is 90% of fs. since the lsb of the least significant bit in the digital reading reg- ister is known, the expected digital results are also known for both inputs (null/lsb = cnt1 and 90%fs/ lsb = cnt2). the user might not directly force a voltage on the input. instead they have a circuit that transforms light, fre- quency, power, or current to a voltage that is the input to the ds1859. in this situation, the user does not need to know the relationship of voltage to expected digital result but instead knows the relationship of light, fre- quency, power, or current to the expected digital result. pos r c ru v c w c xyc zc , , () = + () + () ?? ? ?? ? () + () + () ?? ? ?? ? 12 5 2 5 12 5 2 5 2 2 m6m5 m4 m3 m2 m1 24 68 10 12 temperature ( c) memory location increasing temperature decreasing temperature figure 4. look-up table hysteresis address (hex) variable lsb f8 u 2 0 f9 v 20e-6 fa w 100e-9 fb x 1 2 1 fc x 0 2 -7 fd y 2e-6 (signed) fe z 10e-9 ff reserved downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 23 an explanation of the binary search used to scale thegain is best served with the following example pseudo- code: /* assume that the null input is 0.5v. */ /* in addition, the requirement for lsb is 50?. */ fs = 65535 x 50e-6; /* 3.27675 */ cnt1 = 0.5 / 50e-6; /* 10000 */ cnt2 = 0.90 x fs / 50e-6; /* 58981.5 */ /* thus the null input 0.5v and the 90% of fs input is2.949075v. */ set the trim-offset-register to zero;set right-shift register to zero (typically zero. see right-shifting section); gain_result = 0h;clamp = fff8h/2^(right_shift_register); for n = 15 down to 0 begin gain_result = gain_result + 2^n;force the 90% fs input (2.949075v); meas2 = read the digital result from the part; if meas2 >= clamp then gain_result = gain_result ?2^n; else force the null input (0.5v);meas1 = read the digital result from the part; if (meas2 ?meas1) > (cnt2 ? cnt1) then gain_result = gain_result ?2^n; end;set the gain register to gain_result; the gain register is now set and the resolution of theconversion will best match the expected lsb. the next step is to calibrate the offset of the ds1859. with the correct gain value written to the gain register, again force the null input to the pin. read the digital result from the part (meas1). the offset value is equal to the negative value of meas1. the calculated offset is now written to the ds1859 andthe gain and offset scaling is now complete. right-shifting a/d conversion result (scalable dynamic ranging) the right-shifting method is used to regain some of thelost adc range of a calibrated system. if a system is calibrated such that the maximum expected input results in a digital output value of less than 7fffh (1/2 fs), then it is a candidate for using the right-shifting method. if the maximum desired digital output is less than 7fffh, then the calibrated system is using less than 1/2 of the adc? range. similarly, if the maximum desired digital output is less than 1fffh, then the calibrated system is only using 1/8 of the adc? range. for example, if using a zero for the right-shift during internal calibration and the maximum expected input results in a maximum digi- tal output less than 1ffch, only 1/8 of the adc? range is used. if left like this, the three ms bits of the adc will never be used. in this example, a value of 3 for the right- shifting will maximize the adc range. no resolution is lost since this is a 12-bit converter that is left justified. the value can be right-shifted four times without losing resolution. table 9 shows when the right-shifting method can be used. memory protection memory access from either device address can beeither read/write or read only. write protection is accomplished by a combination of control bits in eeprom (apen and mpen in configuration register 89h) and a write-protect enable (wpen) pin. since the wpen pin is often not accessible from outside the mod- ule, this scheme effectively allows the module to be locked by the manufacturer to prevent accidental writes by the end user. separate write protection is provided for the auxiliary and main device address through distinct bits apen and mpen. apen and mpen are bits from configura- tion register 89h, table 01. due to the location, the apen and mpen bits can only be written through the offset gister h meas xor h _re = ?? ? ?? ? [] 4000 1 2 4000 output range used with zero right-shifts number of right-shifts needed 0h .. ffffh 0 0h .. 7fffh 1 0h .. 3fffh 2 0h .. 1fffh 3 0h .. 0fffh 4 table 9. right shifting downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 24 ____________________________________________________________________ main device address. the control of write privilegesthrough the auxiliary device address depends on the value of apen. care should be taken with the setting of mpen, once set to a 1, assuming wpen is high. access through the main device is thereafter denied unless wpen is taken to a low level. by this means, inadvertent end-user write access can be denied. main device address space 60h to 7fh is sram and is not write protected by apen, mpen, or wpen. for example, the user may reset flags set by the device. note that in single device mode (aden bit = 1), apen determines the protection level of table 00, indepen- dent of wpen. the write-protect operation, for both main and auxiliary devices, is summarized in tables 6 and 7. temperature conversion the direct-to-digital temperature sensor measures tem-perature through the use of an on-chip temperature measurement technique with an operating range from -40? to +102?. temperature conversions are initiated upon power-up, and the most recent conversion is stored in memory locations 60h and 61h of the main device, which are updated every t frame . temperature conversions do not occur during an active read or writeto memory. the value of each resistor is determined by the tempera- ture-addressed look-up table. the look-up table assigns a unique value to each resistor for every 2? increment with a 1? hysteresis at a temperature transition over the operating temperature range (see figure 4). power-up and low-voltage operation during power-up, the device is inactive until v cc exceeds the digital power-on-reset voltage (pod). at thisvoltage, the digital circuitry, which includes the 2-wire interface, becomes functional. however, eeprom- backed registers/settings cannot be internally read (recalled into shadow sram) until v cc exceeds the ana- log power-on-reset voltage (poa), at which time theremainder of the device becomes fully functional. once v cc exceeds poa, the rdyb bit in byte 6eh of the main device memory is timed to go from a 1 to a 0 and indi- cates when analog-to-digital conversions begin. if v cc ever dips below poa, the rdyb bit reads as a 1 again.once a device exceeds poa and the eeprom is recalled, the values remain active (recalled) until v cc falls below pod.for 2-wire device addresses sourced from eeprom (adfix = 1), the device address defaults to a2h until v cc exceeds poa and the eeprom values are recalled. the auxiliary device (a0h) is always available within this volt- age window (between pod and the eeprom recall)regardless of the programmed state of aden. furthermore, as the device powers up, the v cc lo alarm flag (bit 4 of 70h in main device) defaults to a 1 until thefirst v cc analog-to-digital conversion occurs and sets or clears the flag accordingly. 2-wire operation clock and data transitions: the sda pin is normally pulled high with an external resistor or device. data onthe sda pin may only change during scl-low time periods. data changes during scl-high periods will indicate a start or stop condition depending on the conditions discussed below. see the timing diagrams in figures 5 and 6 for further details. start condition: a high-to-low transition of sda with scl high is a start condition that must precede any other command. see the timing diagrams in figures 5 and 6 for further details. stop condition: a low-to-high transition of sda with scl high is a stop condition. after a read or write sequence, the stop command places the ds1859 into a low-power mode. see the timing diagrams in figures 5 and 6 for further details. acknowledge: all address and data bytes are trans- mitted through a serial protocol. the ds1859 pulls the sda line low during the ninth clock pulse to acknowl- edge that it has received each word. standby mode: the ds1859 features a low-power mode that is automatically enabled after power-on, after a stop command, and after the completion of all internal operations. device addressing: the ds1859 must receive an 8-bit device address following a start condition to enable a specific device for a read or write operation. the address is clocked into this part msb to lsb. the address byte consists of either a2h or the value in table 01 8ch for the main device or a0h for the auxiliary device, then the r/ w bit. this byte must match the address programmed into table 01 8ch or a0h (for the auxiliary device). if a device address match occurs, this part will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is enabled (see the memory organization section). if the r/ w bit is high, a read operation is initi- ated. if the r/ w is low, a write operation is initiated (see the memory organization section). if the address does not match, this part returns to a low-power mode. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 25 write operations after receiving a matching address byte with the r/ w bit set low, if there is no write protect, the device goesinto the write mode of operation (see the memory organization section). the master must transmit an 8- bit eeprom memory address to the device to definethe address where the data is to be written. after the byte has been received, the ds1859 transmits a zero for one clock cycle to acknowledge the address has been received. the master must then transmit an 8-bit data word to be written into this address. the ds1859 again transmits a zero for one clock cycle to acknowl- edge the receipt of the data. at this point, the master must terminate the write operation with a stop condi- tion. the ds1859 then enters an internally timed write process t w to the eeprom memory. all inputs are dis- abled during this byte write cycle. page write the ds1859 is capable of an 8-byte page write. a pageis any 8-byte block of memory starting with an address evenly divisible by eight and ending with the starting address plus seven. for example, addresses 00h through 07h constitute one page. other pages would be addresses 08h through 0fh, 10h through 17h, 18h through 1fh, etc. a page write is initiated the same way as a byte write, but the master does not send a stop condition after the first byte. instead, after the slave acknowledges the data byte has been received, the master can send up to seven more bytes using the same nine-clock sequence. the master must terminate the write cycle with a stop condition or the data clocked into the ds1859 will not be latched into permanent memory. the address counter rolls on a page during a write. the counter does not count through the entire address space as during a read. for example, if the starting address is 06h and 4 bytes are written, the first byte goes into address 06h. the second goes into address 07h. the third goes into address 00h (not 08h). the fourth goes into address 01h. if more than 9 bytes or more are written before a stop condition is sent, the first bytes sent are overwritten. only the last 8 bytes of data are written to the page. acknowledge polling: once the internally timed write has started and the ds1859 inputs are disabled,acknowledge polling can be initiated. the process involves transmitting a start condition followed by the device address. the r/ w bit signifies the type of opera- tion that is desired. the read or write sequence will onlybe allowed to proceed if the internal write cycle has completed and the ds1859 responds with a zero. read operations after receiving a matching address byte with the r/ w bit set high, the device goes into the read mode of opera- tion. there are three read operations: current address read, random read, and sequential address read. current address read the ds1859 has an internal address register that main-tains the address used during the last read or write stop condition or repeated start condition repeated if more bytes are transferred ack start condition ack acknowledgement signal from receiver acknowledgement signal from receiver slave address msb scl sda r/w direction bit 12 678 9 12 89 3? figure 5. 2-wire data transfer protocol downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors 26 ____________________________________________________________________ operation, incremented by one. this data is maintainedas long as v cc is valid. if the most recent address was the last byte in memory, then the register resets to thefirst address. once the device address is clocked in and acknowl- edged by the ds1859 with the r/ w bit set to high, the current address data word is clocked out. the masterdoes not respond with a zero, but does generate a stop condition afterwards. single read a random read requires a dummy byte write sequence toload in the data byte address. once the device and data address bytes are clocked in by the master and acknowl- edged by the ds1859, the master must generate another start condition. the master now initiates a current address read by sending the device address with the r/ w bit set high. the ds1859 acknowledges the device address and serially clocks out the data byte. sequential address read sequential reads are initiated by either a currentaddress read or a random address read. after the mas- ter receives the first data byte, the master responds with an acknowledge. as long as the ds1859 receives this acknowledge after a byte is read, the master can clock out additional data words from the ds1859. after reaching address ffh, it resets to address 00h. the sequential read operation is terminated when the master initiates a stop condition. the master does not respond with a zero. the following section provides a detailed description of the 2-wire theory of operation. 2-wire serial-port operation the 2-wire serial-port interface supports a bidirectionaldata transmission protocol with device addressing. a device that sends data on the bus is defined as a trans- mitter, and a device that receives data as a receiver. the device that controls the message is called a mas- ter. the devices that are controlled by the master are slaves. the bus must be controlled by a master device that generates the serial clock (scl), controls the bus access, and generates the start and stop condi- tions. the ds1859 operates as a slave on the 2-wire bus. connections to the bus are made through the open-drain i/o lines sda and scl. the following i/o terminals control the 2-wire serial port: sda, scl. timing diagrams for the 2-wire serial port can be found in figures 5 and 6. timing information for the 2-wire serial port is provided in the ac electrical characteristics table for 2-wire serial communications. the following bus protocol has been defined: data transfer may be initiated only when the bus isnot busy. during data transfer, the data line must remainstable whenever the clock line is high. changes in sdascl t hd:sta t low t high t r t f t buf t hd:dat t su:dat repeated start t su:sta t hd:sta t su:sto t sp stop start figure 6. 2-wire ac characteristics downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors ____________________________________________________________________ 27 the data line while the clock line is high will beinterpreted as control signals. accordingly, the following bus conditions have beendefined: bus not busy: both data and clock lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid data when, after a start condition, the data line is sta- ble for the duration of the high period of the clock signal. the data on the line can be changed during the low peri- od of the clock signal. there is one clock pulse per bit of data. figures 5 and 6 detail how data transfer is accom- plished on the 2-wire bus. depending on the state of the r/ w bit, two types of data transfer are possible. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between start and stop con- ditions is not limited and is determined by the master device. the information is transferred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications, a standard mode (100khz clock rate) and a fast mode (400khz clock rate) are defined. the ds1859 works in both modes. acknowledge: each receiving device, when addressed, is obliged to generate an acknowledge after the bytehas been received. the master device must generate an extra clock pulse, which is associated with this acknowl- edge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge-related clock pulse. setup and hold times must be taken into account. a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. 1) data transfer from a master transmitter to aslave receiver. the first byte transmitted by the master is the command/control byte. next followsa number of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a mas-ter receiver. the master transmits the first byte (the command/control byte) to the slave. the slave then returns an acknowledge bit. next fol- lows a number of data bytes transmitted by the slave to the master. the master returns an acknowledge bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge can be returned. the master device generates all serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since a repeated start condition is also the beginning of the next serial transfer, the bus is not released. the ds1859 can operate in the following three modes: 1) slave receiver mode: serial data and clock are received through sda and scl, respectively. after each byte is received, an acknowledge bit is trans- mitted. start and stop conditions are recog- nized as the beginning and end of a serial transfer. address recognition is performed by hardware after the slave (device) address and direction bit have been received. 2) slave transmitter mode: the first byte is received and handled as in the slave receivermode. however, in this mode the direction bit indicates that the transfer direction is reversed. serial data is transmitted on sda by the ds1859, while the serial clock is input on scl. start and stop conditions are recognized as the beginning and end of a serial transfer. 3) slave address: command/control byte is the first byte received following the start condition from the master device. the command/control byte consists of 4-bit control code. they are used by the master device to select which of eight possi- ble devices on the bus is to be accessed. when reading or writing to the ds1859, the device- select bits must match one of two valid device addresses, 00h or the address registered in table 01 location 8ch. the last bit of the command/con- trol byte (r/ w ) defines the operation to be per- formed. when set to a ??a read operation isselected, and when set to a ??a write operation is selected. the slave address can be set by the eeprom. following the start condition, the ds1859 monitors the sda bus checking the device type identifier being transmitted. upon receiving the 1010 control code, the appropriate device address bits, and the read/write bit, the slave device outputs an acknowledge signal on the sda line. downloaded from: http:///
ds1859 dual, temperature-controlled resistors with internally calibrated monitors maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 28 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2006 maxim integrated products printed usa is a registered trademark of maxim integrated products, inc. is a registered trademark of dallas semiconductor corporation. chip information transistor count: 47,191substrate connected to ground package information for the latest package outline information, go towww.maxim-ic.com/dallaspackinfo . ordering information (continued) part resistance pin-package ds1859b-050+t&r 50k ? 16 csbga ds1859b-050/t&r 50k ? 16 csbga ds1859e-020 20k ? 16 tssop ds1859e-020+ 20k ? 16 tssop ds1859e-020/t&r 20k ? 16 tssop ds1859e-020+t&r 20k ? 16 tssop ds1859e-050 50k ? 16 tssop ds1859e-050+ 50k ? 16 tssop ds1859e-050+t&r 50k ? 16 tssop ds1859e-050/t&r 50k ? 16 tssop + denotes lead-free package. t&r denotes tape-and-reel package. downloaded from: http:///

▲Up To Search▲

Price & Availability of DS1859E-015

	To Download DS1859E-015 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .